1. Field of Invention
The present invention relates to a memory device. More particularly, the present invention relates to a flash memory structure and operating method thereof.
2. Description of Related Art
Flash memory is a device having multiple data access, read-out and erase capability. Furthermore, data stored within a flash memory will be retained even after power to the device is cut off. Hence, flash memory has become one of the most popular non-volatile memories deployed inside personal computers and electronic equipment.
A typical flash memory device has a floating gate and a control gate fabricated using doped polysilicon. The control gate is set up over the floating gate with the two layers separated from each other by a dielectric layer. The floating gate is isolated from an underlying substrate by a tunneling oxide layer, thereby forming a stack gate flash memory structure.
To write data into the flash memory, a bias voltage is applied to the control gate and the source/drain region and hence electrons are injected into the floating gate. To read data from the flash memory, an operating voltage is applied to the control gate. With the charging condition inside the floating gate affecting the conductive state of the channel, a value of “0” or “1” can be determined. To erase data from the flash memory, relative potential of the substrate, the drain (source) region or the control gate is raised. Through action caused by a tunneling effect, trapped electrons inside the floating gate penetrate through the tunneling oxide layer into the substrate or the drain (source) terminal (the so-called substrate erase or drain (source) side erase) or penetrate through the dielectric layer into the control gate.
However, the quantity of electrons bled out from the floating gate is difficult to control in an operation to erase data from the flash memory. If an excessive amount of electrons flows out of the floating gate, the floating gate will contain a net positive charge leading to an over-erase condition. If such over-erase phenomena is severe, the channel underneath the floating gate may conduct without the application of an operating voltage resulting in erroneous reading. To reduce the over-erasing problem, most flash memory has a split-gate design. One major aspect of a split-gate design is the addition of a select gate (or erase gate) on the sidewall of the control gate and the floating gate and above the substrate besides the control gate and the floating gate. The selective gate (or erase gate) is isolated from the control gate, the floating gate and the substrate through a gate dielectric layer. When over-erase is severe so that the channel underneath the floating gate is conductive even without applying an operating voltage to the control gate, the channel underneath the select gate still remains shut. In other words, the source/drain region is non-conductive and erroneous reading from the flash memory is prevented. Nevertheless, a split-gate structure demands a larger area and hence each memory cell has a larger dimension compared with a conventional stack gate flash memory. That means, overall level of integration has to be reduced. To reduce the size of each memory cell, a dual-cell flash memory structure with two cells using the same select gate is invented.
FIG. 1 is a schematic cross-sectional view of a conventional dual-cell flash memory structure. The dual-cell flash memory structure in FIG. 1 includes a first memory cell 101a and a second memory cell 101b over a substrate 100. The first memory cell 101a has a gate structure 102a that includes a tunneling oxide layer 104a, a floating gate 106a, a gate dielectric layer 108a, a control gate 110a and a cap layer 112a. Similarly, the second memory cell 101b has a gate that includes a tunneling oxide layer 104b, a floating gate 106b, a gate dielectric layer 108b, a control gate 110b and a cap layer 112b. Spacers 114a and 114b are attached to the sidewalls of the first gate structure 102a and the second gate structure 102b respectively. Source/drain regions 116a and 116b are located in the substrate 100 on opposite sides of the first gate structure 102a and the second gate structure 102b. A select gate 118 not only covers the gate structures 102a, 102b but also extends from one source/drain region 116a to another source/drain region 116b. 
To program data into the memory cell 101a of the dual-cell flash memory structure, the memory cell 101b serves as a channel transistor. A bias voltage of 10V is applied to the control gate 110a; a bias voltage of 10V is applied to the control gate 110b so that the channel underneath the memory cell 101b is opened; a bias voltage of 2V is applied to the select gate 118; a bias voltage of 2V is applied to the source/drain region 116a and a bias voltage of 0V is applied to the source/drain region 116b. With this voltage setup, electrons moving from the source/drain region 116b towards the source/drain region 116a are accelerated by the intense electric field close to the source/drain region 116a to generate hot electrons. Kinetic energy of these electrons overcomes the energy barrier in the tunneling oxide layer 104a, and together with the high positive bias voltage applied to the control gate 110a, the hot electrons are injected into the floating gate 106a from the source/drain region 116a. Hence, the memory cell 101a is programmed. Similarly, to program data into the memory cell 101b of the dual-cell flash memory structure, the memory cell 101a serves as a channel transistor. A bias voltage of 10V is applied to the control gate 110b; a bias voltage of 10V is applied to the control gate 110a so that the channel underneath the memory cell 101a is opened; a bias voltage of 2V is applied to the select gate 118; a bias voltage of 2V is applied to the source/drain region 116b and a bias voltage of 0V is applied to the source/drain region 116a. With this voltage setup, electrons moving from the source/drain region 116a towards the source/drain region 116b are accelerated by the intense electric field close to the source/drain region 116b to generate hot electrons. Kinetic energy of these electrons overcomes the energy barrier in the tunneling oxide layer 104b, and together with the high positive bias voltage applied to the control gate 110b, the hot electrons are injected into the floating gate 106b from the source/drain region 116b. Hence, the memory cell 101b is programmed.
In the aforementioned method of programming a dual-cell flash memory structure, if the memory cell 101b is programmed immediately after programming the memory cell 101a, the memory cell 101b may be affected by the programmed memory cell 101a leading to a lowering of programming current. Hence, programming speed of the memory cell 101b will be lower than the memory cell 101a. In other words, the dual-cell flash memory will have an unsymmetrical programming operation resulting in a slower overall operating speed.